Axiom's CDF is a new age functional verification automation tool. It focuses users (verification engineers, designers, architects .) on the most important aspect - the specifications and the verification plan, while taking away manual verification vector creation efforts from them. This technology will result in substantial reduction of chip design cycle and cost for design houses. By creating an Executable Verification Plan using Axiom's CDF, users will offload two painful and demanding processes to the CDF tool suite -

Features

• Constraint Specification
• Coverage Specification

CDF automatically synthesizes 'Constraint Trees' and 'Functional Coverage Points' based on the Executable Verification Plan, shaving off significant time and efforts from the critical and demanding verification activity. The CDF methodology is -.

• Creation and sign-off of 'Executable Verification Plan'
• Attaching CDF to regressions

Once these 2 steps are accomplished, CDF Verification Automation tool suite will automatically create optimal, controlled vectors set ready to be used by the Testbench to drive transactions into the design. The verification engineers can then spend more time looking at test failures and design issues rather than working on constraint refinement. Since CDF provides a highly simplified user interface, the creation and review of Executable Verification Plan will require significantly less time and efforts compared to the creation of constraints or vectors themselves. Axiom has been able to successfully train its customers' engineers (including designers and architects) to create and review CDF based Executable Verification Plans very quickly. CDF also brings in a host of utilities to manage vector generation and coverage. Users have access to CDF-supported Hybrid Convergence Methodology for quick and controlled functional verification closure.

CDF is Testbench Implementation Independent and can be applied to SystemC, Verilog, SystemVerilog or HVL based Testbenches and even to Hardware Accelerators and Emulation boxes. It can be easily packaged into Bus Functional Models to create a wrapper of Executable Verification Plan, which can be customized at the users' level without needing access to the BFM source code. CDF can be applied at block, sub-system and system level verification without needing to change the Testbench, with the constraints & coverage history being carried through all stages of ASIC design.

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