Designer delivers next generation graphical debugging and design analysis environment. Designer helps to quickly isolate functional errors during creation, formal model checking, simulation and synthesis of Verilog-based designs.

It includes powerful new features that are currently not available in other commercial debuggers. With Designer, you can carry out extensive simulation post-processing, including:

• Execution Tracing - identify the lines of RTL code being evaluated at specific time points.
• Memory Content Tracing - view the contents of memory as it changes during simulation, by easily moving forward and backward in time.

• Source code and memory breakpoints – view in post-processing mode

Designer Advantages

• Designer can work with any simulator in all the existing environments seamlessly
• Integrated TestBench & RTL Source Browsing and debugging
• Assertion-based coverage analysis and debugging for both simulation & formal model checking

• Execution and Memory tracing
• Source-code and memory break pointing
• Powerful search engine and automatic inference engine
• Extensive Clock Analysis
• Programmable Design Rule Checker
• Incremental Cone Viewing
• Incremental Pipeline Viewing
• Active driver/receiver tracing from source or waveform
• Execution tracing
• Memory viewer – does not require dumping memory during simulations
• Intelligent X-Tracing mode expands through active logic to find sources of unknown values
• User-defined radices and expressions
• Signal grouping
• DRC, Coverage, Expression Coverage and Clock Domain View