MPSim is the industry’s first multi-CPU simulator.  Providing a competitive performance on single CPU platforms, MPSim truly accelerates simulation performance on multi-CPU machines.  In situations where waveforms have to be viewed as soon as possible, the multi-CPU MPSim with its native waveform dump support offers un-matched performance.  AXIOM’s MPSim is a complete verification environment combining the fastest simulator in the industry with advanced testbench automation, UPF support, assertion-based verification, debugging, as well as formal and coverage analysis.

Features

• Native Multi-Processor Support
• Compiled Test Bench support for OpenVera & SystemVerilog
• Single kernel support for multiple languages – HDL & HVL
• Native support for UPF for power aware simulation
• Integrated debugging environment with schematic & cone viewing, driver / receiver tracing, X tracing, memory viewer etc
• In-built code coverage – includes line, conditional, expression coverage
• OpenVera & SystemVerilog based functional coverage
• Protometer CDF based protocol level coverage
• Fast kernel level signal dumping
• Support for SVA, OVA and PSL assertions

Native Multi-Processor Support -
CPUs have undergone a massive shift from their previous emphasis on increased clock speeds to their current focus on multi processing and multiple cores.

AXIOM’s MPSim is the first and only simulator architected from the ground-up to take advantage of these new multi-CPU hardware platforms, without requiring any change in existing products or methodologies and with no limitations on design style or capacity, while at the same time providing an integrated verification environment.

Compiled TestBench (CTB)
MPSim has built-in support for advanced testbench features provided by SystemVerilog and the OpenVera™ Hardware Verification language including:

• Classes
• Inheritance and Virtualization
• Interfaces, clocking and virtual ports
• Built-in structures like Arrays, Associative arrays, lists and queues
• Constrained randomization
• Communication structures like Mailboxes, semaphores etc.

All of these features are supported using the unified compiled data model, resulting in up to 5X faster performance than interpreted solutions. The AXIOM constrained random solver engines are based on

advanced AXIOM formal verification products and are guaranteed to find solutions when they exist. By utilizing a compiled constraint solution approach, the AXIOM constraint solver can produce results significantly faster than other tools

CTB Advantages

• Powerful functional coverage analysis
• Integrated Support for SystemVerilog Testbench
• Support for SystemVerilog and OpenVera™
• Integrated debugging environment

UPF
The MPSim solution provides full support of the UPF format including power-off corruption, setting isolation signals, specifying retention capabilities for state-machines, as well as enhanced capabilities within its suite of debug tools and coverage of the power control mechanisms specified in the design and UPF file.

UPF provides a single low-power description that can be used in the design and verification process and fosters tool interoperability. Without a single low-power description, each step of the design process would need to rely on the error-prone and cumbersome process of translating multiple formats and proprietary commands, where the power intent could easily deviate from each other. Now design engineers using Magma's IC implementation system and the verification engineer using the MPSim verification environment can use the same low-power description.

Powerful Integrated Debugging
The Designer graphical debugging tool offers advanced debugging features including:

• Active driver / receiver tracing in source browser and waveform viewer
• Graphical waveform viewer, including advanced features such as custom radices, signal grouping and regexp searching.
• Execution Tracing, Value Annotation and Tooltip
• Schematic and logic cone viewing
• Intelligent X-tracing
• Memory Viewer

Integrated RTL Design Rule Checker
With MPSim’s Multi-CPU capability, each CPU can dump out waveform data independently and Designer can merge all waveform files providing a transparent interface to the user, as if the simulation was running on a single CPU.

MPSim Advantages

• Ability to uncover corner case bugs in the design that would have been otherwise undetected, by generating significantly greater vectors in the same period of time as alternative products
• Fastest simulator in industry, providing ability to run long tests in days instead of weeks
• Increases designer's day time productivity by improving waveform dumping and simulation performance
• Integrated debugging of design, testbench and assertions
• Plug & Play compatible with existing products and methodologies with no limitations on design style or design capacity

Language and Hardware Support
MPSim supports SystemVerilog 3.1a, IEEE Verilog 1364-2001, PSL, SystemC and PLI. MPSim runs on 32bit and 64bit Linux and Solaris workstations.