Verifier - For designs with multiple, asynchronous clock domains, it is virtually impossible to detect errors in synchronization by merely using simulation. Verifier's clock domain analysis tools, provides both structural and functional checks, combined with a friendly, easy to use graphical interface to debug issues.

Verifier detects the toughest design problems by an innovative application of Formal Model Checking and Automatic Functional Vector Generation. Verifier automatically extracts properties from RTL to unravel problems including:

• Multiple clock domain synchronization errors
• Finite State Machine (FSM) deadlock
• Code reachability errors

In addition to detecting these difficult problems, the automatic property extraction inherent in Verifier can find an extensive set of other bugs, including one-hot drivers and decoders, parallel and full case statements, unreachable and terminal state, never reachable conditions and codes, FIFO read/write and reset errors, index-out-of range and stuck at zero/one.

Verifier Advantages

• Advanced solver technology for Incremental, Hierarchical and Distributed Processing assertions
• IBM rule based solver provides higher capacity for more difficult assertions
• Automatic assertions make assertion-based verification easy to deploy for the design team by
  • Finding bugs earlier on in the design cycle
  • Allowing verification of constraints given to static timing analysis
  • Helping assertion development through Designer-PRO
  • Visualizing waveform, testing against dump file, running in formal/simulation, debugging failed assertion
  • Distributing processing of assertions across existing server farms to greatly decrease turn-around time