DEB: Dynamic Event Balancing
Up until recently, digital simulators were riding the wave of faster CPUs to get performance increases.
As the machines got faster, simulation ran faster. But then the CPU clock speeds reached a plateau and there was no significant performance improvements in the new generation of hardware. Computer designers then introduced multi-CPU architecture with the idea of speeding up applications by distributing the application over multiple CPUs and executing them in parallel. It was a natural evolution for EDA vendors to try to exploit this multi-core architecture to speed up EDA applications.
Many vendors tried to port their simulators, which was originally designed to run on a single CPU to multi-CPU architecture, and met with mixed results. This is because RTL and logic simulation involves complex algorithms with sequence of events happening over a period of time. Distributing a design over multiple CPUs does not always result in increased performance. In fact, if the partitioning is not done correctly, the simulation performance could even be slower.
The challenge is that at compile time, information on
event activity is not available. Using heuristics to statically partition the design does not always work. This is the main reason multi core simulators do not always provide added performance over single CPU simulation. To overcome this challenge, Axiom pioneered the Dynamic Event Balancing (DEB) technology. MPSim is the first and only simulator that was targeted from scratch for multi-CPU architecture, incorporating Axiom’s proprietary DEB technology.
DEB technology involves a special engine that analyzes the activity during simulation and dynamically partitions the design such that the activity is evenly distributed over multiple CPUs. Since activity is dependent on the testbench, DEB’s auto-learn mode creates different partitions for different testbenches which can be used later during regressions for truly multi-core optimized execution.
DEB’s real advantage is realized during regressions, which is one of the most time consuming phase in the verification cycle. With the Auto Learn Mode turned on, MPSim collects information on the event activity for each test even on a single CPU simulation. During regression on multi-CPU machines, this information is used to intelligently partition the design such that event activity is evenly distributed among the CPUs.
The result is significant increase in performance. Direct benefit resulting from the increased performance is that 3 -10 X more tests can be run with MPSim on a multi-core machine compared to running simulation on a single CPU in the same amount of time.
In addition to event balancing, memory allocation is also optimized to avoid collisions and bottlenecks. Memory assignments are made at run time and relocated as needed during simulation. The result is a highly optimized partition that takes full advantage of the multi-core architecture for highest simulation performance.
Waveform dumping has been known to significantly slow down simulation on a single CPU. In MPSim waveform dumping is also distributed over multiple CPUs to maximize throughput.
DEB also does a smart distribution of associated applications such as testbench execution, waveform dumping, coverage analysis and assertions checking. Together with optimized design partitioning, MPSim’s multi-core technology offers the highest simulation performance on multi-CPU machines.